This invention relates generally to integrated circuit memories and more particularly to memories having a relatively large storage capacity.
As is known in the art, it is generally desirable to increase the memory storage capacity of integrated circuit memories. However, as the memory capacity of the integrated circuit increases the power requirements of the circuit correspondingly increases. For example, in a bipolar read-only memory (ROM) circuit the cross points of rows and columns of conductors correspond to the memory locations of the circuit. The presence, or absence, of an electrical connection between the row and column conductors at a particular cross point determines the logical state of the bit stored at the corresponding memory location. Once programmed, the data is read from a particular location by coupling address signals to row and column decoders to select the particular row and column conductors which "cross" at the addressed location. As is known in the art, for such memory circuit these decoders generally require power for their operation and, as the size or capacity of the memory circuit increases, the size of the decoders correspondingly increase in order to provide addressing to an increased number of rows and columns of conductors. More particularly, the decoders generally include logic gates and diode matrices so that when a larger number of gates and/or matrices is used in the decoders, extra power is consumed by the additional resistors in such gates and matrices. One way which may be used to decrease the power consumption of the increased capacity decoders is to increase the resistance of these resistors; however, the increased resistance increases the switching time of the decoder thereby resulting in a more slowly responding ROM circuit.